Reduced Instruction Set Computer Architectures for VLSI

The Reduced Instruction Set Computer (RISC) concept is an important new way of optimizing computer architecture. This book demonstrates the practicality of the RISC approach. Integrated circuits offer compact and low-cost implementation of digital systems, and provide performance gains through their high-bandwidth on-chip communication. In a single chip microcomputer, however, the implementation trade-offs are different from those in traditional broad-based main frame computers. Because the total silicon area and the amount of allowable power dissipation are strictly limited, extra resources added to speed up some function of the chip will typically slow down other operations. This work demonstrates that the recent trend in computer architecture toward the use of increasingly complex instruction sets leads to the inefficient use of those scarce resources. Reduced Instruction Set Computer architectures offer an alternative by allowing for the effective use of on-chip transistors in functional units that provide fast access to frequently used operands and instructions. Contents: Introduction (the RISC Concept, Effective Use of Hardware Resources, Evolution of the Berkeley RISC Project); The Nature of General Purpose Computations; The RISC I and 11 Architecture and Pipeline; The RISC II Design and Layout; Debugging and Testing RISC II; Additional Hardware Support for General-Purpose Computations; Conclusions; Appendix A: Detailed Description of the RISC 11 Architecture. Manolis G. H. Katevenis received his doctorate from the University of California at Berkeley. He is currently Assistant Professor of Computer Science at Stanford University. Reduced Instruction Set Computer Architectures for VLSI is the winner of the 1984 Doctoral Dissertation Award.